An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).
Once information is stored in a memory location, it is found by comparing every bit in a memory location with corresponding bits in a comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, a local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which desired data is stored or identification of one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back an address if there is a match found in memory.
FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell 100, which includes two one-transistor (1T) DRAM cells 110a and 110b, and a four-transistor comparator circuit 120 made up of transistors Q2 through Q5. Although FIG. 1 illustrates a DRAM-based CAM cell, it should be recognized that CAM devices can also be made using SRAM-based CAM cells. DRAM cells 110a and 110b are used to store values. Generally, the content of cell 110a is the logical NOT of the content of cell 110b. However, the cells 110a, 110b may also store the same values, i.e., “0”/“0”, or “1”/“1”, so that the CAM cell is respectively set to “always match” or “always mismatch” states. DRAM cell 110a includes transistor Q1 and a capacitor CA, which combine to form a storage node A that receives a data value from bitline BL1 at node U during write operations, and applies the stored data value to the gate terminal of transistor Q2 of comparator circuit 120. Transistor Q2 is connected in series with transistor Q3, which is controlled by a data signal transmitted on data line D1#, between a matchline M and ground potential. It should be noted that in some embodiments transistors Q2 and Q4 are coupled to a discharge line instead of being directly coupled to ground. The second DRAM cell 110b includes transistor Q6 and a capacitor CB, which combine to form a storage node B that receives a data value from bitline BL2 at node V, and applies the stored data value to the gate terminal of transistor Q4 of comparator circuit 120. Transistor Q4 is connected in series with transistor Q5, which is controlled by a data signal transmitted on inverted data line D1, between the matchline and the ground potential.
FIG. 2 is a block diagram of a portion of a CAM device 200 which includes a plurality of CAM cells, such as the CAM cell 100 of FIG. 1. For purposes of simplicity, only a portion of the CAM device 200 is illustrated. In particular, some well known components, such as the previously discussed comparand register, control logic, and I/O logic are not illustrated. The device 200 includes two arrays 210a, 210b of CAM cells 100. Each array 210a, 210b includes its own bitlines (e.g., BL11–BL16 for array 210a, and BL21–BL26 for array 210b), wordlines (e.g., WL11–WL12 for array 210a), and matchlines (e.g., M11–M12 for array 210a). Each wordline WL11–WL12, WL21–WL22 is coupled to a respective wordline driver 220a, 220b. Similarly, each bitline is also coupled to respective bitline drivers (not illustrated). Each matchline is coupled to each row of CAM cell 100 in the same wordline. The CAM device 200 also includes a plurality of bitline sense amplifiers 230. Each bitline sense amplifier 230 is coupled to the CAM cells 100 from two different arrays by two separate bitlines (e.g. bitlines BL11, BL21).
Now referring back to FIG. 1, in order perform a write operation upon a CAM cell, the data values (which are complements) to be stored are respectively written to dynamic storage nodes A and B by applying appropriate voltage signals (e.g., Vcc for logical ‘1’ or ground for logical ‘0’) on bitlines BL11 and BL12, and then applying a voltage signal on wordline WL. The voltage on wordline WL turn on transistor Q1 and Q6, thereby passing the voltage signals to dynamic storage nodes A and B. Refresh circuitry (not illustrated), periodically refreshes the charges stored in capacitors CA and CB, so the data does not decay over time.
In order to perform a read operation, data stored as a charge level in the capacitors CA, CB of one of the dynamic storage nodes A, B of the CAM cell 100 is sensed using an associated sense amplifier 230 (FIG. 2) which compares the voltage level of a bitline coupled to one of the dynamic storage nodes (known as the active bitline) with the voltage level of a bitline not coupled to any dynamic storage nodes (known as the reference bitline). For example, node A of the CAM cell 100 which appears as the top left CAM cell illustrated in FIG. 2 can be sensed by first precharging two bitlines. The two bitlines to be precharged would include the bitline BL11 which will couple the CAM cell 100 to the sense amplifier 230 (i.e., the active bitline), as well as the other bitline BL21 coupled to the same sense amplifier 230 (i.e., the reference bitline). As illustrated in FIG. 2, each sense amplifier has one input coupled to a bitline of array 210a and another input coupled to a corresponding bitline of array 210b. The wordline WL12 associated with the CAM cell 100 would then be activated by an applied voltage, causing the transistor Q1 in the CAM cell 100 to conduct and thereby share the charge of capacitor CA with bitline BL1. Depending upon the charge level stored in capacitor CA, the voltage level of bitline BL11 will either remain the same or be lowered. The sense amplifier 230 is then used to detect whether there is a change in potential between BL11 and BL21. The sense amplifier outputs an indication of the state stored at storage node A as a signal indicating any potential difference between bitlines BL11 and BL21 on line 235.
In order to perform a match operation, the data stored at nodes A and B are respectively applied to the gate terminals of transistors Q2 and Q4 of comparator circuit 120. Comparator circuit 120 is utilized to perform match (comparison) operations after the matchline M has been precharged by a precharge circuit (not illustrated). For example, when matchline M is precharged, an applied data value and its complement are transmitted on data lines D1 and D1# to the gate terminals of transistor Q3 and Q5, respectively. A no-match condition is detected when matchline M is discharged to ground through the signal path formed by transistors Q2 and Q3, or through the signal path formed by transistors Q5 and Q4. For example, when the stored data value at node A and the applied data value transmitted on data line D1# are both logic “1”, then both transistors Q2 and Q3 are turned on to discharge matchline M to ground. When a match condition occurs, matchline M remains in its pre-charged state (i.e., no signal path is formed by transistors Q2 and Q3, or transistors Q5 and Q6).
The above described match operation is directed to what happens in a single CAM cell 100. In a real CAM device, however, the match operation is performed simultaneously on all CAM cells. In contrast, a conventional memory device, such as a DRAM, does not directly support a match function and must therefore be operated in accordance with a search algorithm to sequentially search each memory location for in order to perform the same function. Thus search operations are typically performed much faster by a CAM device. However, CAM devices consume significantly more power and produce significantly more switching noise than a conventional memory device, especially during search operations because CAM cells are accessed simultaneously. Additionally, the current flow through each matchline varies based on how well the CAM cells associated with the matchline match the search expression. This is because each CAM cell which does not match its respective search data will form a pull down path between the matchline and ground, while each CAM cell which matches it respective search data will not form a pull down path between the matchline and ground. In CAM devices each matchline is typically coupled to a large number of CAM cells. The number of pull down paths on a matchline can therefore vary greatly during a search. Thus, the rate which a matchline can be discharged will can also vary greatly. This range in current flow in each matchline, especially when compounded by differences caused by variations in semiconductor process, power supply voltage variations, and temperature variations makes sensing the state of each matchline M a difficult procedure. Accordingly, there is a need for a CAM device architecture having a matchline sensing mechanism which is relatively immune to the number of CAM cells which match on a search operation.